Pack instruction

ABSTRACT

A processor executes an instruction that causes a source data field from a first source register to be copied to a destination register at a programmable position within the destination register. The instruction is particularly useful for generating media-based bitstreams (e.g., audio, video). In some embodiments, a system (e.g., a communication device such as cellular telephone) includes a processor capable of executing the instruction as described above.

CROSS REFERENCE TO RELATED CASES

This application claims the benefit of European Patent Application No. 04291918.3, filed Jul. 27, 2004, incorporated by reference herein as if reproduced in full below.

BACKGROUND

1. Technical Field

The present subject matter relates generally to processors and more particularly to an executable instruction that copies at least a portion of the contents of a register to a destination register at a programmable location within the destination register.

2. Background Information

Many types of electronic devices are battery operated and thus preferably consume as little power as possible. An example is a cellular telephone. Further, it may be desirable to implement various types of multimedia functionality in an electronic device such as a cell phone. Examples of multimedia functionality may include, without limitation, games, audio decoders, digital cameras, etc. It is thus desirable to implement such functionality in an electronic device in a way that, all else being equal, is fast, consumes as little power as possible and requires as little memory as possible. Improvements in this area are desirable.

BRIEF SUMMARY

In at least one embodiment, a processor executes an instruction that causes a source data field from a first source register to be copied to a destination register at a programmable position within the destination register. In some embodiments, a system (e.g., a communication device such as cellular telephone) includes a processor capable of executing the instruction as described above.

In another embodiment, a method of executing an instruction is disclosed that comprises examining the instruction to determine a first source register, examining the instruction to determine a destination register, and determining a position associated with the destination register. The method further comprises copying a source data field from the first source register to a portion of the destination register defined by the position, without affecting other portions of the destination register.

In general, the instruction is useful to create a bitstream from multiple input values. For example, 9 variables of 3 bits each and one 5-bit variable could be packed into a single 32-bit register in a specific configuration of the various variables. The instruction can be used in some embodiments for generating, for example, media-based bitstreams (e.g., audio, video).

NOTATION AND NOMENCLATURE

Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, various companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to.” Also, the term “couple” or “couples” is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more detailed description of the preferred embodiments of the present invention, reference will now be made to the accompanying drawings, wherein:

FIG. 1 shows a diagram of a system in accordance with preferred embodiments of the invention and including a Java Stack Machine (“JSM”) and a Main Processor Unit (“MPU”);

FIG. 2 illustrates an embodiment of the invention in the form of a wireless communication device such as a cellular telephone;

FIG. 3 shows a block diagram of the JSM of FIG. 1 in accordance with preferred embodiments of the invention;

FIG. 4 shows various registers used in the JSM;

FIG. 5 shows a function performed by a PACK instruction in accordance with the preferred embodiment of the invention; and

FIGS. 6 and 7 show exemplary formats of the PACK instruction in accordance with a preferred embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims, unless otherwise specified. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.

The subject matter disclosed herein is directed to a programmable electronic device such as a processor that executes various instructions including, without limitation, a “PACK” instruction. As will be explained in detail below, the PACK instruction permits the creation of a bit stream by copying some or all of the contents of a source register to a designated location within a destination register. The PACK instruction is particularly useful for generating, for example, media-based bitstreams (e.g., audio, video). The following describes the operation of a preferred embodiment of a processor on which the PACK instruction may run. Other processor architectures and embodiments may be available or developed on which to run the instruction and thus this disclosure and the claims which follow are not limited to any particular type of processor. Details regarding the operation and format of the PACK instruction follow the description of the processor.

The processor described herein is particularly suited for executing Java TM Bytecodes or comparable code. As is well known, Java is particularly suited for embedded applications. Java is a relatively “dense” language meaning that on average each instruction may perform a large number of functions compared to various other programming languages. The dense nature of Java is of particular benefit for portable, battery-operated devices that preferably include as little memory as possible to save space and power. The reason, however, for executing Java code is not material to this disclosure or the claims which follow. The processor described herein may be used in a wide variety of electronic systems. By way of example and without limitation, the Java-executing processor described herein may be used in a portable, battery-operated communication device such as a cellular telephone, personal data assistants (“PDAs”), etc. Further, the processor advantageously includes one or more features that permit the execution of the Java code to be accelerated.

Referring now to FIG. 1, a system 100 is shown in accordance with a preferred embodiment of the invention. As shown, the system includes at least two processors 102 and 104. Processor 102 is referred to for purposes of this disclosure as a Java Stack Machine (“JSM”) and processor 104 may be referred to as a Main Processor Unit (“MPU”). System 100 may also include memory 106 coupled to both the JSM 102 and MPU 104 and thus accessible by both processors. At least a portion of the memory 106 may be shared by both processors meaning that both processors may access the same shared memory locations. Further, if desired, a portion of the memory 106 may be designated as private to one processor or the other. System 100 also includes a Java Virtual Machine (“JVM”) 108, compiler 110, and a display 114. The JSM 102 and/or MPU 104 preferably includes an interface to one or more input/output (“I/O”) devices such as a keypad to permit a user to control various aspects of the system 100. In addition, data streams may be received from the I/O space into the JSM 102 to be processed by the JSM 102. Other components (not specifically shown) may include, without limitation, a battery and an analog transceiver to permit wireless communications with other devices. As noted above, while system 100 may be representative of, or adapted to, a wide variety of electronic systems, an exemplary electronic system may comprise a battery-operated, mobile cell phone such as that is shown in FIG. 2.

As shown in FIG. 2, a mobile communications device includes an integrated keypad 412 and display 414. Two processors and other components may be included in electronics package 410 connected to keypad 412, display 414, and radio frequency (“RF”) circuitry 416 which may be connected to an antenna 418.

As is generally well known, Java code comprises a plurality of “bytecodes” 112. Bytecodes 112 may be provided to the JVM 108, compiled by compiler 110 and provided to the JSM 102 and/or MPU 104 for execution therein. In accordance with a preferred embodiment of the invention, the JSM 102 may execute at least some, and generally most, of the Java bytecodes. When appropriate, however, the JSM 102 may request the MPU 104 to execute one or more Java bytecodes not executed or executable by the JSM 102. In addition to executing Java bytecodes, the MPU 104 also may execute non-Java instructions. The MPU 104 also hosts an operating system (“O/S”) (not specifically shown), which performs various functions including system memory management, system task management for scheduling the JVM 108 and most, or all, other native tasks running on the system, management of the display 114, receiving input from input devices, etc. Without limitation, Java code may be used to perform any one of a variety of applications including multimedia data processing, games or web-based applications, while non-Java code, which may comprise the O/S and other native applications, may still run on the system on the MPU 104.

The JVM 108 generally comprises a combination of software and hardware. The software may include the compiler 110 and the hardware may include the JSM 102. The JVM may include a class loader, bytecode verifier, garbage collector, and a bytecode interpreter loop to interpret the bytecodes that are not executed on the JSM processor 102.

In accordance with preferred embodiments of the invention, the JSM 102 may execute at least two instruction sets. One instruction set may comprise standard Java bytecodes. As is well-known, Java is a stack-based programming language in which instructions generally target a stack. For example, an integer add (“IADD”) Java instruction pops two integers off the top of the stack, adds them together, and pushes the sum back on the stack. The JSM 102 comprises a stack-based architecture with various features that accelerate the execution of stack-based Java code, such as those described in U.S. patent Pub. Nos. 2004/0078550, 2004/0078557, and 2004/0024999, all of which are incorporated herein by reference.

Another instruction set executed by the JSM 102 may include instructions other than standard Java instructions. In accordance with at least some embodiments of the invention, such other instruction set may include register-based and memory-based operations. This other instruction set generally complements the Java instruction set and, accordingly, may be referred to as a complementary instruction set architecture (“CISA”). By complementary, it is meant that the execution of one or more Java bytecodes may be substituted by “microsequences” using CISA instructions that enable faster, more efficient operation. The two sets of instructions may be used in a complementary fashion to obtain satisfactory code density and efficiency. As such, the JSM 102 generally comprises a stack-based architecture for efficient and accelerated execution of Java bytecodes combined with a register-based architecture for executing register and memory based CISA instructions. Both architectures preferably are tightly combined and integrated through the CISA.

FIG. 3 shows an exemplary block diagram of the JSM 102. As shown, the JSM includes a core 120 coupled to data storage 122 and instruction storage 130. The core may include one or more components as shown. Such components preferably include a plurality of registers 140, address generation units (“AGUs”) 142, 147, micro-translation lookaside buffers (micro-TLBs) 144, 156, a multi-entry micro-stack 146, an arithmetic logic unit (“ALU”) 148, a multiplier 150, decode logic 152, and instruction fetch logic 154. In general, operands may be retrieved from data storage 122 or from the micro-stack 146 and processed by the ALU 148, while instructions may be fetched from instruction storage 130 by fetch logic 154 and decoded by decode logic 152. The address generation unit 142 may be used to calculate addresses based, at least in part, on data contained in the registers 140. The AGUs 142 may calculate addresses for CISA instructions. The AGUs 142 may support parallel data accesses for CISA instructions that perform array or other types of processing. AGU 147 couples to the micro-stack 146 and manages overflow and underflow conditions in the micro-stack, preferably in parallel. The micro-TLBs 144, 156 generally perform the function of a cache for the address translation and memory protection information bits that are preferably under the control of the operating system running on the MPU 104.

Referring now to FIG. 4, the registers 140 may include 16 registers designated as R0-R15. All registers are 32-bit registers in accordance with the preferred embodiment of the invention. Registers R0-R5 and R8-R14 may be used as general purpose (“GP”) registers, thereby usable for any purpose by the programmer. Other registers, and at least one of the GP purpose registers, may be used for specific functions. For example, in addition to use as a GP register, register R5 may be used to store the base address of a portion of memory in which Java local variables may be stored when used by the current Java method. The top of the micro-stack 146 is reflected in registers R6 and R7. The top of the micro-stack has a matching address in memory pointed to by register R6. The values contained in the micro-stack are the latest updated values, while their corresponding values in memory may or may not be up to date. Register R7 provides the data value stored at the top of the micro-stack. Register R15 is used for status and control of the JSM 102.

Referring again to FIG. 3, as noted above, the JSM 102 is adapted to process and execute instructions from at least two instruction sets. One instruction set includes stack-based operations and the second instruction set includes register-based and memory-based operations. The stack-based instruction set may include Java bytecodes. Java bytecodes pop, unless empty, data from and push data onto the micro-stack 146. The micro-stack 146 preferably comprises the top n entries of a larger stack that is implemented in data storage 122. Although the value of n may vary in different embodiments, in accordance with at least some embodiments, the size n of the micro-stack may be the top eight entries in the larger, memory-based stack. The micro-stack 146 preferably comprises a plurality of gates in the core 120 of the JSM 102. By implementing the micro-stack 146 in gates (e.g., registers) in the core 120 of the processor 102, access to the data contained in the micro-stack 146 is generally very fast, although any particular access speed is not a limitation on this disclosure.

The second, register-based, memory-based instruction set may comprise the CISA instruction set introduced above. The CISA instruction set preferably is complementary to the Java bytecode instruction set in that the CISA instructions may be used to accelerate or otherwise enhance the execution of Java bytecodes. For example, the compiler 110 may scan a series of Java bytes codes 112 and replace one or more of such bytecodes with an optimized code segment mixing CISA and bytecodes and which is capable of more efficiently performing the function(s) performed by the initial group of Java bytecodes. In at least this way, Java execution may be accelerated by the JSM 102. The CISA instruction set includes a plurality of instructions including a “PACK” instruction as mentioned above and explained below in detail.

Referring still to FIG. 3, the ALU 148 adds, subtracts, and shifts data. The multiplier 150 may be used to multiply two values together in one or more cycles. The instruction fetch logic 154 generally fetches instructions from instruction storage 130. The instructions are decoded by decode logic 152. Because the JSM 102 is adapted to process instructions from at least two instruction sets, the decode logic 152 generally comprises at least two modes of operation, one mode for each instruction set. As such, the decode logic unit 152 may include a Java mode in which Java instructions may be decoded and a CISA mode in which CISA instructions may be decoded. In a preferred embodiment, the decode logic provides the capability to decode, in a given mode, an instruction associated with the other mode without penalty using a specific prefix.

The data storage 122 generally comprises data cache (“D-cache”) 124 and data random access memory (“D-RAMset”) 126. Reference may be made to U.S. patent Publications Ser. No. 09/591,537 filed Jun. 9, 2000 (atty docket TI-29884), Ser. No. 09/591,656 filed Jun. 9, 2000 (atty docket TI-29960), Ser. No. 09/932,794 filed Aug. 17, 2001 (atty docket TI-31351), and U.S. patent Pub. No. 20040260904, all of which are incorporated herein by reference, for information related to the D-RAMset. The stack (excluding the micro-stack 146), arrays and non-critical data may be stored in the D-cache 124, while Java local variables, critical data and non-Java variables (e.g., C, C++) may be stored in D-RAMset 126. The instruction storage 130 may comprise instruction RAM (“I-RAM”) 132 and instruction cache (“I-cache”) 134.

One of the CISA instructions, as noted above, is the “PACK” instruction. The function performed by the PACK instruction is illustrated in FIG. 5. As shown, the function performed by the PACK instruction is to copy the contents of a source data field 200 from the lowest order bits of a source register (Rs1) to a destination register (Rd) at a location identified by a position value P. The identity of registers Rs1 and Rd, the size m of source data field 200, and the position value P preferably are all programmable. In the embodiment of FIG. 5, the value of P is contained in another source register Rs2. The size of the source data field 200 in source register Rs1 is m bits and the value of m is included as a field within the PACK instruction itself. The various fields in the PACK instruction will be explained below with regard to FIGS. 6 and 7. By executing the PACK instruction, a bit stream can be created (“packed”) in destination register Rd in increments of m bits at a time. Once the destination register Rd contains all of the data it is desired to contain, the contents of register Rd can be submitted for further processing.

As shown in FIG. 5, a portion of destination register Rd is altered upon the inclusion of data source field 200. That is, the bits that begin at position P and extend for m bits in register Rd changed to the state of the corresponding bits from source field 200 in register Rs1. The remaining bits in the destination register Rd remain unaffected by the newly copied source data field. That is, fields 201 and 203 remain unchanged by the inclusion of field 200.

Multiple embodiments of a PACK instruction are possible. Two such embodiments are depicted in FIGS. 6 and 7. The state of bit 15 differentiates the two versions of the PACK instruction in FIGS. 6 and 7. A “0” in bit 15 designates the PACK instruction embodiment of FIG. 6, while a “1” designates the PACK instruction embodiment of FIG. 7.

As shown in FIG. 6, the PACK instruction is a 32-bit instruction, although the number of bits for the instruction can be varied as desired. In the embodiment of FIG. 6, the PACK instruction comprises fields 250-266. Field 250 comprises an instruction class field 250 that identifies the class to which the instruction pertains. Some classes may have only a single instruction pertaining thereto and thus the instruction class field 250 identifies the particular instruction (similar to an opcode). The PACK instruction pertains to an instruction class that includes multiple instructions including PACK and other instructions. In this situation, the particular instruction is identified by the OpX1 value in field 266. Thus, the OpX1 value in FIG. 6 is a value that uniquely identifies the instruction as a PACK instruction. Moreover, the instruction class fields 250 and OpX1 fields 266 are the same between FIGS. 6 and 7, and the differentiation between the two versions of PACK results from the status of field 258 (bit 15) as explained above.

Bits 24 through 27 (field 252) comprises a 4-bit field that identifies the particular register to be used as the destination register Rd. As shown in FIG. 4, multiple registers can function as general purpose registers and thus can function as the destination register Rd. The source register Rs1, from which the source data field 200 originates, is designated by bits 20 through 23 (field 254) in the instruction and can be one of the GP registers in FIG. 4.

Bits 16 through 19 (field 256) specify the other source register Rs2 which contains the position value P to which the source data field 200 is to be copied in register Rd. The position value P designates the lowest order bit to which the source data field 200 is to be copied in register Rd. In other embodiments, the position value P may specify the highest order bit in register Rd to which the source data field 200 is to be copied. As for the source register Rs1, source register Rs2 containing the P value is preferably one of the general purpose registers depicted in FIG. 4.

Bit 14 (field 260) is unused in a PACK instruction and set to a value of 0 in FIGS. 6 and 7. Bits 9 through 13 (field 262) not used in the particular embodiment of PACK depicted in FIG. 6. As such, bits 9 to 13 are set at a value of 0. The PACK instruction embodiment of FIG. 7 does use bits 9 through 13 as will be explained below. The value of m, which defines the width of the source data field 200 (i.e., the number of bits of field 200), is provided in bits 4 through 8 (field 264) of the PACK instruction. As a 5-bit value, m can specify a width from 1 bit to 32 bits. As the registers are 32-bit registers in the embodiments described herein, an m value of 32 means that the entire contents of source register Rs1 is to be copied to destination register Rd. Of course, it is incumbent to the programmer to ensure that the position value P permits there to be a sufficient number of bit positions to copy the source data field 200 in its entirety given the specified value of m. In the case in which the value of P does leave enough bits in Rd to accommodate all of the source data field 200 (e.g., P points to bit 30 in Rd, but source field 200 contains 5 bits), then the lowest order bits of the source field 200 that will fit in Rd are written, and all extra bits of the source field 200 are ignored.

In FIG. 5 the position value P comes from the second source register Rs2 which is identified by field 256 in the PACK instruction format of FIG. 6. FIG. 7 shows another format for the PACK instruction. The format of FIG. 7 is similar to that of FIG. 6 in that the same fields are provided for the instruction class and OpX1 values, the identity of the destination register Rd, the identity of the source register Rs1 containing the source data field 200, and the value of m defining the size of the source data field 200. Field 256 (bits 16 through 19), however, no longer identify a second source register Rs2 for the P value. Instead field 262 (bits 9 through 13) include the position value P itself rather than a pointer to a register that contains the P value.

In the embodiments described above, the value of m is contained in the instruction itself. In other embodiments, the instruction may contain an identifier of a register that contains the value of m. For example, rather than bits 4 through 8 containing the value of m, those bits could identify the register from among the register set (FIG. 4) that contains the value of m. Further, bit 14 could be encoded so as to specify whether bits 4 through 8 contain m (e.g., bit 14=1_ or an identifier of the register that encodes m (e.g., bit 14=0).

In still another embodiment of the PACK instruction, the value of P is contained in the instruction itself (similar to the embodiment of FIG. 7) and bit 15 is used to specify whether the instruction contains the value of m or rather the instruction contains an identifier of a register that contains the value of m (as explained above). In other words bit 15 (or bit 14 for that matter) could be used in a similar fashion as described above to differentiate the two versions of the PACK instruction, but rather than differentiating where to find the value of P while in both versions the instruction always contains the value of m, the two versions could differentiate where to find the value of m while the instruction always contains the value of P. Moreover, in various embodiments, m and P are programmable as to their source location.

As noted above, the PACK instruction permits one or more of the least significant bits from a designated source register to be copied to a desired position within a designated destination register. The PACK instruction provides flexibility to specify the source register that contains the data field to be copied, the size of the data field to be copied, the destination register into which the data field is to be copied and the position within the destination register at which the data field is to be copied.

The PACK instruction described herein permits a bit stream to be formed in an efficient, quick manner. The PACK instruction can be executed multiple times to copy multiple source data fields to various locations within a destination register.

While the preferred embodiments of the present invention have been shown and described, modifications thereof can be made by one skilled in the art without departing from the spirit and teachings of the invention. The embodiments described herein are exemplary only, and are not intended to be limiting. Many variations and modifications of the invention disclosed herein are possible and are within the scope of the invention. Accordingly, the scope of protection is not limited by the description set out above. Each and every claim is incorporated into the specification as an embodiment of the present invention. 

1. A processor executing a plurality of instructions, comprising: an arithmetic logic unit (ALU); and a plurality of registers coupled to the ALU; wherein said processor executes an instruction that causes a source data field from a first source register to be copied to a destination register at a programmable position within the destination register.
 2. The processor of claim 1 wherein the position is programmable by a position value provided within the instruction.
 3. The processor of claim 1 wherein the position is programmable by a position value contained in a second source register.
 4. The processor of claim 3 wherein the instruction includes a pointer to the second source register.
 5. The processor of claim 1 wherein the instruction includes a pointer to the first source register.
 6. The processor of claim 1 wherein the instruction includes a pointer to the destination register.
 7. The processor of claim 1 wherein the instruction comprises a size value that specifies a size of the source data field in the first source register.
 8. The processor of claim 1 wherein the instruction comprises an identifier of a register that contains a size value that specifies a size of the source data field in the first source register.
 9. The processor of claim 1 wherein the position is other than a least significant bit of the destination register.
 10. The processor of claim 1 wherein the source data field is of a size that is less than a size of the destination register and all bits in the destination register that lie outside the bits of the bits of the source data field copied into the destination register are not changed when the source data field is copied into the destination register.
 11. A method of executing an instruction, comprising: examining the instruction to determine a first source register; examining the instruction to determine a destination register; determining a position associated with the destination register; and copying a source data field from the first source register to a portion of the destination register defined by the position, without affecting other portions of the destination register.
 12. The method of claim 11 wherein determining the position comprises examining a position value contained in the instruction.
 13. The method of claim 11 wherein determining the position comprises examining a position value contained in a second source register identified in the instruction.
 14. The method of claim 11 further comprising examining the instruction to determine a size of the source data field to copy in the first source register to copy to the destination register.
 15. A system, comprising: a main processor unit; and a co-processor coupled to said main processor unit, wherein said co-processor executes an instruction that causes a source data field from a first source register to be copied to a destination register at a programmable position within the destination register.
 16. The system of claim 15 wherein the position is programmable by a position value provided within the instruction.
 17. The system of claim 15 wherein the position is programmable by a position value contained in a second source register that is identified in the instruction.
 18. The system of claim 15 wherein the instruction includes a pointer to the first source register.
 19. The system of claim 15 wherein the instruction includes a pointer to the destination register.
 20. The system of claim 15 wherein the instruction comprises a size value that specifies a size of the source data field in the first source register.
 21. The system of claim 15 wherein the instruction comprises an identifier of a register that contains a size value that specifies a size of the source data field in the first source register.
 22. The system of claim 15 wherein the system comprises a communication device. 